Altium

Design Rule Verification Report

Date: 2/1/2018
Time: 5:31:39 PM
Elapsed Time: 00:00:00
Filename: D:\Google Drive\Git Repos\personal-coding\Altium Projects\Blinky\Blinky.PcbDoc
Warnings: 0
Rule Violations: 23

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=6mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 13
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=8mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=7mil) (All) 0
Hole Size Constraint (Min=16mil) (Max=251mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 10
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 23

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net NetR3_2 Between Pad R3-2(2050mil,464.646mil) on Multi-Layer And Pad U1-3(2390mil,230mil) on Multi-Layer
Un-Routed Net Constraint: Net NetR1_1 Between Pad U1-7(2690mil,330mil) on Multi-Layer And Pad R1-1(2810mil,392.599mil) on Top Layer
Un-Routed Net Constraint: Net NetR1_1 Between Pad R2-1(2210mil,392.599mil) on Top Layer And Pad U1-7(2690mil,330mil) on Multi-Layer
Un-Routed Net Constraint: Net NetLED_1 Between Pad LED-1(1660mil,420mil) on Multi-Layer And Pad R3-1(2050mil,130mil) on Multi-Layer
Un-Routed Net Constraint: Net NetC1_2 Between Pad R2-2(2210mil,467.402mil) on Top Layer And Pad U1-2(2390mil,330mil) on Multi-Layer
Un-Routed Net Constraint: Net NetC1_2 Between Pad C1-2(1890mil,467.402mil) on Top Layer And Pad R2-2(2210mil,467.402mil) on Top Layer
Un-Routed Net Constraint: Net NetC1_2 Between Pad U1-2(2390mil,330mil) on Multi-Layer And Pad U1-6(2690mil,230mil) on Multi-Layer
Un-Routed Net Constraint: Net VCC Between Pad U1-8(2690mil,430mil) on Multi-Layer And Pad R1-2(2810mil,467.402mil) on Top Layer
Un-Routed Net Constraint: Net VCC Between Pad R1-2(2810mil,467.402mil) on Top Layer And Pad J1-1(2980mil,440mil) on Multi-Layer
Un-Routed Net Constraint: Net VCC Between Pad U1-4(2390mil,130mil) on Multi-Layer And Pad U1-8(2690mil,430mil) on Multi-Layer
Un-Routed Net Constraint: Net GND Between Pad LED-2(1760mil,420mil) on Multi-Layer And Pad C1-1(1890mil,392.599mil) on Top Layer
Un-Routed Net Constraint: Net GND Between Pad C1-1(1890mil,392.599mil) on Top Layer And Pad U1-1(2390mil,430mil) on Multi-Layer
Un-Routed Net Constraint: Net GND Between Pad U1-1(2390mil,430mil) on Multi-Layer And Pad J1-2(2980mil,340mil) on Multi-Layer
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Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (6.429mil < 10mil) Between Arc (1710mil,420mil) on Top Overlay And Pad LED-1(1660mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.429mil]
Silk To Solder Mask Clearance Constraint: (6.429mil < 10mil) Between Arc (1710mil,420mil) on Top Overlay And Pad LED-1(1660mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.429mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (2785mil,430mil)(2835mil,430mil) on Top Overlay And Pad R1-2(2810mil,467.402mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (2785mil,430mil)(2835mil,430mil) on Top Overlay And Pad R1-1(2810mil,392.599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (2185mil,430mil)(2235mil,430mil) on Top Overlay And Pad R2-2(2210mil,467.402mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (2185mil,430mil)(2235mil,430mil) on Top Overlay And Pad R2-1(2210mil,392.599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (1865mil,430mil)(1915mil,430mil) on Top Overlay And Pad C1-2(1890mil,467.402mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (1865mil,430mil)(1915mil,430mil) on Top Overlay And Pad C1-1(1890mil,392.599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (1.038mil < 10mil) Between Track (1758.209mil,455mil)(1758.209mil,476.953mil) on Top Overlay And Pad LED-2(1760mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [1.038mil]
Silk To Solder Mask Clearance Constraint: (1.038mil < 10mil) Between Track (1758.209mil,363.047mil)(1758.209mil,385mil) on Top Overlay And Pad LED-2(1760mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [1.038mil]
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